The present invention relates to a display drive device including a plurality of cascade connected drive circuits for driving a display element such as a liquid crystal display element according to an image data signal, and further relates to a liquid crystal module incorporating such a display drive device.
A display drive device used in a conventional liquid crystal display device includes, as shown in FIG. 14, source driver LSI (Large Scale Integrated circuit) chips 51 and gate driver LSI chips 52 that are cascade connected and mounted on individual TCPs (Tape Carrier Packages) 53 to act as a plurality of drive circuits for driving a liquid crystal panel 54. Further, the display drive device, together with the liquid crystal panel 54, constitutes a liquid crystal module. Note that a TCP refers to a thin package including a tape film onto which an LSI chip is attached.
The source driver LSI chips 51 and the gate driver LSI chips 52 have output terminals electrically connected via TCP wiring on the TCPs 53 to output terminals of the TCPs 53 for output to the liquid crystal panel 54. The output terminal of the TCPs 53 to the liquid crystal panel 54 is bonded by thermocompression via, for example, an ACF (Anisotropic Conductive Film) to a terminal (not shown) fabricated from ITO (Indium Tin Oxide) on the liquid crystal panel 54 to establish electrical connection therebetween. The liquid crystal panel 54 here is supposed to have 800xc3x973 (RGB) [source side]xc3x97600 [gate side] pixels.
Each of the source driver LSI chips 51 drives 100xc3x973 (RGB) pixels, and performs a 64 half-tone display. Therefore, here, eight source driver LSI chips 51 are cascade connected. Hereinafter, to distinguish each of the source driver LSI chips 51 from the others, those located in first to seventh stages will be referred to as first to seventh source drivers respectively, with the source driver LSI chip 51 located in the last stage referred to as an eighth source driver.
Meanwhile, two gate driver LSI chips 52 are cascade connected here. Hereinafter, to distinguish each of the gate driver LSI chips 52 from the other, those located in first and last stages will be referred to as first and second gate drivers respectively.
The display drive device includes a flexible substrate 55 on which a controller 56 is disposed; the TCPs 53 are electrically connected to the flexible substrate 55. Specifically, the TCP wiring on the TCPs 53 that is electrically connected to the source driver LSI chips 51 and the gate driver LSI chips 52 is electrically connected via, for example, an ACF or soldering to the wiring on the flexible substrate 55 that is electrically connected to output terminals R, G, B, LS, Vcc, GND, Vref, VLS, SSPI, SCK, GCK, and GSPI (see FIG. 15) of the controller 56.
This configuration allows various signals to travel to and from the source and gate driver LSI chips 51 and 52 through the wiring on the TCPs 53 and the flexible substrate 55. The following description will explain various signal paths in the liquid crystal module.
First, the controller 56 provides, as outputs, image data signals R, G, and B at its output terminals R, G, and B, a clock signal CK at its output terminal SCK, and a latch signal LS at its output terminal LS; all these signals are then transmitted via the wiring on the flexible substrate 55 and the TCPs 53, and supplied as common signals to each of the source driver LSI chips 51.
Meanwhile, the controller 56 provides at its output terminal SSPI an output of a start pulse signal SPI which is transmitted via the wiring on the flexible substrate 55 and coupled to an input terminal SPin of the first source driver. After receiving the start pulse signal SPI, the first source driver transmits the start pulse signal SPI internally and provides an output of a start pulse signal SPO at its output terminal SPout. The output start pulse signal SPO is transmitted again via the wiring on the flexible substrate 55 and is coupled to input of a following stage, that is, an input terminal SPin of the second source driver. The start pulse signal SPI is similarly shifted and transmitted through further source drivers, until it reaches the last stage, that is, the eighth source driver.
Similarly, the controller 56 provides, as outputs, an LSI chip power supply voltage Vcc at its output terminal Vcc, 64 bit half-tone display reference voltages Vref1 to Vref6 at its output terminals Vref1 to Vref6, and a brightness adjusting voltage (voltage for adjusting the voltage applied to the liquid crystal panel 54) VLS at its output terminal VLS; all these signals, as well as a ground potential GND electrically connected to the output terminal GND of the controller 56, are supplied commonly to each of the source driver LSI chips 51. The wiring for transmitting the voltages Vcc, Vref1 to Vref6, and VLS and the ground connection line (GND line) for transmitting the ground potential GND are disposed as power supply associated lines. Hereinafter, the voltages Vcc, Vref1 to Vref6, and VLS, and the ground potential GND will be referred to as power supply associated voltages.
Meanwhile, the controller 56 provides, as outputs, a gate driver clock signal GCK at its output terminal GCK, an LSI chip power supply voltage Vcc at its output terminal Vcc, and reference voltages Vref 1 and 2 (Vref1 and Vref2) at its output terminals Vref 1 and 2 for application to the liquid crystal panel 54; all these signals, as well as a ground potential GND electrically connected to an output terminal GND of the controller 56, are supplied commonly to each of the gate driver LSI chips 52.
Further, the controller 56 provides at its output terminal GSPI an output of a gate driver start pulse signal GSPI which is coupled to an input terminal GSPin of the first gate driver. The first gate driver transmits the received start pulse signal GSPI internally in synchronization with the clock signal GCK and provides at its output terminal GSPout a start pulse signal GSPO which is coupled to an input terminal GSPin of a following stage, that is, of the second gate driver.
The following description will explain in detail a circuit arrangement of the source driver LSI chips 51 in accordance with the present invention in reference to the block diagram constituting FIG. 16 and also explain in detail operations of the source driver LSI chips 51 in reference to the signal timing charts constituting FIG. 17. Note that although the following description will deal with only one of the eight source driver LSI chips 51 shown in FIG. 14, all the source driver LSI chips 51 function completely identically.
As shown in FIG. 16, the source driver LSI chip 51 is arranged to include a shift register 61, a data latch circuit 62, a sampling memory 63, a hold memory 64, a reference voltage generator circuit 65, a D/A converter 66, and an output circuit 67.
The shift register 61 receives the start pulse signal SPI (see FIG. 17) provided as an output by the controller 56 at its output terminal SSPI and transmitted via the input terminal SPin of the source driver LSI chip 51. The start pulse signal SPI is a synchronized signal having synchronization with horizontal synchronized signals of later-mentioned image data signals R, G, and B. The shift register 61 also receives the clock signal CK (see FIG. 17) provided as an output by the controller 56 at its output terminal SCK and transmitted via the input terminal CKin of the source driver LSI chip 51.
The shift register 61 shifts the received start pulse signal SPI: more particularly, the shift register 61 starts shifting the start pulse signal SPI, with the start pulse signal SPI as a start pulse, when the clock signal CK received rises for the first time while the start pulse signal SPI is in high level.
The start pulse signal SPI shifted by the shift register 61 is provided as an outgoing start pulse signal SPO (see FIG. 17) by the source driver LSI chip 51 at its output terminal SPout, and coupled to the input terminal SPin of the following-stage source driver LSI chip 51. The start pulse signal SPI is similarly shifted by further source driver LSI chips, until it reaches the last stage source driver LSI chip 1, that is, the eighth source driver shown in FIG. 14.
Meanwhile, the image data signals R, G, and B (see FIG. 17) supplied by the controller 56 via its respective R, G, and B terminals are coupled as parallel inputs to the data latch circuit 62 via input terminals R1in to R6in, G1in to G6in, and B1in to B6in of the source driver LSI chip 51 as shown in FIG. 16. The image data signals R, G, and B are then temporarily latched by the data latch circuit 62 and transmitted to the sampling memory 63. Note that the image data signals R, G, and B are color digital image signals representing a 6-bit R (Red) set of data, a 6-bit G (Green) set of data, and a 6-bit B (Blue) set of data, collectively representing 18-bit data.
The sampling memory 63 performs sampling on the image data signals R, G, and B transmitted in a time division manner as output signals from the stages in the shift register 61, and stores the sampled signals until a later-mentioned latch signal LS (see FIG. 17) supplied by the controller 56 via its output terminal LS is received.
The hold memory 64 then receives inputs of the image data signals R, G, and B, and latches the signals at a trailing edge of the latch signal LS upon reception of a set of data for a horizontal period. The hold memory 64 holds the set of data for a horizontal period carried on the image data signals R, G, and B, until reception of a set of data for a next horizontal period from the sampling memory 63. During that period, the hold memory 64 provides the image data signals R, G, and B for output to the D/A converter 66. Here, the shift register 61 and the sampling memory 63 receive a new set of image data signals R, G, and B for a next horizontal period.
The reference voltage generator circuit 65 produces 64 levels used for a half-tone display by, for example, resisance division according to the reference voltages Vref1 to Vref6 which are provided as outputs by the controller 56 at its output terminals Vref1 to Vref6 and then coupled to the input terminals Vref1 to Vref6 of the source driver LSI chip 51.
The D/A converter 66 converts the image data signals R, G, and B, which are 6-bit R, G, and B digital image signals respectively, into analog signals. The output circuit 67 then amplifies the analog signals of 64 levels using the brightness adjusting voltage VLS which is provided as an output by the controller 56 at its output terminal VLS and then coupled to the input terminal VLS of the source driver LSI chip 51. Thereafter the output circuit 67 provides, at its output terminals XO1 to XO100, YO1 to YO100, and ZO1 to ZO100, the amplified signals which will be coupled to input terminals (not shown) of the liquid crystal panel 54.
The output terminals XO1 to XO100 constitute a terminal group of 100 terminals for the image data signals R, the output terminals YO1 to YO100 for the image data signals G, and the output terminals ZO1 to ZO100 for the image data signals B. Also, the terminals Vcc and GND of the source driver LSI chip 51 are for providing a power supply to the source driver LSI chip 51. Note that input and output buffer circuits are omitted in FIG. 16.
As mentioned so far, according to the conventional technology, a liquid crystal module is formed by cascade connecting the source driver LSI chips 51 on the TCPs 53 and supplying common and other various signals and power supply associated voltages via the flexible substrate 55, etc. to the source driver LSI chips 51.
However, recent years have seen progressively strong demand from the market for less costly and more compact liquid crystal modules. An offer to this demand is a liquid crystal module with no flexible substrate 55 to accommodate common wires, which in FIG. 14 is included, and in some cases with no print substrate that is used in place of the flexible substrate 55.
The omission of the flexible substrate 55 is made possible in the liquid crystal module by, in the arrangement shown in FIG. 14, electrically connecting adjacent TCPs 53 and employing internal wiring made of, for example, Al (aluminum) lines in the source driver LSI chips 71 (explained in detail later) to allow common signals and power supply associated voltages to be transmitted internally in the TCPs 53.
FIG. 18 shows a block diagram of a source driver LSI chip 71 used for such a liquid crystal module. Here, for convenience, members that have the same function as those shown in FIG. 14 are indicated by the same reference numerals and description thereof is omitted.
The source driver LSI chip 71 is, as shown in Figure 18, identical to the source driver LSI chip 51, except that in the source driver LSI chip 71, additional output terminals R1out to R6out, G1out to G6out, B1out to B6out, LSout, Vref1out to Vref6out, VLS, Vcc, and GND are provided to supply common signals and power supply associated voltages and also that these additional output terminals are electrically connected via internal wiring to input terminals R1in to R6in, G1in to G6in, B1in to B6in, LSin, Vref1in to Vref6in, VLS, Vcc, and GND.
The configuration allows common signals including image data signals R, G, and B and a latch signal LS, and power supply associated voltages including half-tone display reference voltages Vref1 to Vref6, a brightness adjusting voltage VLS, a power supply voltage Vcc, and a ground potential GND to be transmitted internally through the source driver LSI chip 71.
In other words, first, similarly to the arrangement shown in FIG. 14, the common signals R, G, B, and LS and the power supply associated voltages Vref1 to Vref6, VLS , Vcc and GND are fed from a controller (not shown) to the first source driver via the input terminals R1in to R6in, G1in to G6in, B1in to B6in, LSin, Vref1in to Vref6in, VLS, Vcc, and GND.
After being fed to the first source driver, the common signals R, G, B, and LS and the power supply associated voltages Vref1 to Vref6, VLS, Vcc, and GND travel via the internal wiring and appear as outputs at the output terminals R1out to R6out, G1out to G6out, B1out to B6out, LSout, Vref1out to Vref6out, VLS, Vcc, and GND of the first source driver. The common signals R, G, B, and LS and the power supply associated voltages Vref1 to Vref6, VLS, Vcc, and GND supplied by the first source driver are transmitted over electrical connections between adjacent TCPs 53 to be coupled to input terminals R1in to R6in, G1in to G6in, B1in to B6in, LSin, Vref1in to Vref6in, VLS, Vcc, and GND of a following stage, that is, of a second source driver.
Then, similarly to the foregoing, the common signals R, G, B, and LS and the power supply associated voltages Vref1 to Vref 6, VLS, Vcc, and GND are coupled to the input terminals R1in to R6in, G1in to G6in, B1in to B6in, LSin, Vref1in to Vref6in, VLS, Vcc, and GND of the third to eighth source drivers as the signals are transmitted sequentially from the second source driver to the eighth source driver, that is, the last source driver.
The components in the source driver LSI chip 71 operate in the same manner as those in the source driver LSI chip 51: for example, the source driver start pulse signal SPI is coupled as an input to the input terminal Spin, and shifted by the internal shift register 61 in synchronization with a clock signal CK to provide an output of a start pulse signal SPO at the output terminal Spout.
As shown schematically in FIG. 18, in the source driver LSI chip 71, the output terminals XO1 to XO100, YO1 to YO100, and ZO1 to ZO100 to the liquid crystal panel 54 are disposed along a side, whereas the input terminals Spin, CKin, R1in to R6in, G1in to G6in, B1in to B6in, LSin, Vref1in to Vref6in, VLSin, Vcc, and GND are disposed along one of the two sides crossing that side, and the output terminals SPout, CKout, R1out to R6out, G1out to G6out, B1out to B6out, LSout, Vref1out to Vref6out, VLS, Vcc, and GND are disposed along the other of the two sides. Here, input and output buffer circuits are omitted in FIG. 18.
FIG. 19 illustrates, as an example, an arrangement of a liquid crystal module on which the source driver LSI chips 71 are mounted. The members other than the source driver LSI chips 71 and the liquid crystal panel 54 are all omitted from the illustration.
The TCP wiring 53a of adjacent TCPs 53 is electrically connected with each other via source driver connection wiring 54d on the liquid crystal panel 54 so that the TCP wiring 53a disposed on the flanks of the TCPs 53 on which the source driver LSI chips 71 are mounted is electrically connected with each other. The xe2x80x9cflanksxe2x80x9d refer to those when the liquid crystal panel 54 is viewed in the front.
This electrical connection is achieved by disposing the source driver connection wiring 54d made of ITO, the same material as the pixel terminals are made of, on a liquid crystal glass substrate 54a, which is a lower glass of the liquid crystal panel 54, and bonding the TCPs 53 onto the liquid crystal glass substrate 54a via an ACF by thermocompression simultaneously with the establishment of the aforementioned connection between the TCP wiring 53a on the TCPs 53 and the terminals on the liquid crystal panel 54.
In the liquid crystal module, a controller (not shown) is mounted to another flexible substrate so as to be electrically connected to source driver connection wiring 4d on the liquid crystal panel 54.
Note that the TCP wiring 53a on the flanks of the TCPs 53 is electrically connected to the input terminals SPin, CKin, R1in to R6in, G1in to G6in, B1in to B6in, LSin, Vref1in to Vref6in, VLS, Vcc, and GND and to the output terminals SPout, CKout, R1out to R6out, G1out to G6out, B1out to B6out, LSout, Vref1out to Vref6out, VLS, Vcc, and GND, whereas FIG. 19 shows only four lines of the TCP wiring 53a. Note also that FIG. 19 shows only two lines of the source driver connection wiring 54d that, however, actually is constituted by the number of lines that corresponds to the input terminals SPin, CKin, R1in to R6in, G1in to G6in, B1in to B6in, LSin, Vref1in to Vref6in, VLS, Vcc, and GND.
According to this method, the source driver connection wiring 54d on the liquid crystal panel 54 is used to electrically connect adjacent TCPs 53. Alternatively, the TCP wiring 53a of adjacent TCPs 53 may be stacked one over the other to electrically connect those adjacent TCPs 53. The method of stacking the TCP wiring 53a of adjacent TCPs 53 to establish connection between the TCP wiring 53a is disclosed in Japanese Laid-Open Patent Application No. 6-3684/1994 (Tokukaihei 6-3684: published on Jan. 14, 1994) filed by the same applicants as the present application.
As explained in the foregoing, the flexible substrate (or printed substrate) for supplying common signals and power supply associated voltages to the source driver LSI chips 71 becomes dispensable if the common signals and power supply associated voltages transmitted between adjacent TCPs 53 via the TCP wiring 53a and the internal wiring of the source driver LSI chips 71. The elimination of the flexible substrate hence allows the liquid crystal module to be reduced in price and size.
However, new schemes are essential to meet strong commercial needs for even cheaper and more compact liquid crystal modules. Therefore, to reduce the total cost of the liquid crystal module, the size and number of the circuits and wires included in the display drive device with a controller are required be reduced to a greatest possible extent.
In view of the foregoing conventional problem, the present invention has an object to offer a display drive device that has a reduced overall size including a controller and other members, and that can be built at a reduced cost, and has another object to offer a liquid crystal module using such a device.
To achieve the objects, a display drive device of the present invention includes a plurality of cascade connected drive circuits for driving a display element in accordance with an image data signal, each of the drive circuits including a hold memory for latching a predetermined amount of the time division incoming image data signal in accordance with a latch signal, each of the drive circuits converting the latched image data signal to an analog signal and supplying the analog signal to the display element, wherein a latch signal generator circuit for generating the latch signal is disposed in one of the drive circuits which is in a last stage.
With the arrangement, a plurality of drive circuits are cascade connected to drive a display element in accordance with an image data signal. Specifically, each of the drive circuits has a hold memory for latching a predetermined amount of the time division incoming image data signal in accordance with a latch signal, and the image data signal latched by the hold memory is converted to analog and supplied to the display element.
Unlike conventional display drive devices, the display drive device is capable of internally generating a latch signal in the foregoing manner, and can dispense with an external supply of a latch signal by a controller or the like. Therefore, the display drive device can dispense with circuits, in an external circuit, associated with the latch signal, output terminals of the external circuit, and latch signal transmitting wiring for electrically connecting the external circuit to the display drive device, which are all required with a conventional display drive device to supply a latch signal from the external circuit. This arrangement enables the display drive device, including a controller, etc., to be produced in a reduced overall size and at a lower cost.